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Andes Technology’s N9 CPU embedded into smart speaker

Andes Technology’s N9 CPU embedded into smart speaker
Andes Technology, a Taiwan-based supplier of small, low-power and high performance 32/64-bit embedded CPU cores, recently announced that its N9 CPU IP is designed into an IC design house’s SoC.

This chip is embedded in a voice-controlled artificial intelligence (AI) device from one of the world’s largest online retailers. The AndesCore N9’s high-performance efficiency and low interrupt latency enable the customer’s SoC to provide wireless connectivity for the 2.4GHz WiFi/Bluetooth, 5GHz WiFi, GPS, and FM radio front ends.

The integration makes the chip in great demand in the cost sensitive and small-form factor consumer smart speaker AI devices. These smart speaker AI devices feature hands-free, voice control to play music, control smart home devices, make calls, send and receive messages, provide information, read the news, set alarms, read audiobooks, control video, etc.

Andes President Frankwell Jyh-Ming Lin, said, “In highly integrated chips like this SoC, our ability to provide 3.6 CoreMark/MHz compute performance while consuming 80% of the program memory size of its competitors gives Andes a distinct advantage.

Furthermore, the N9 allows designers to configure its performance, power and size to match their applications’ requirement more precisely. These capabilities have enabled the N9 to win a number of wireless connectivity designs, Lin added.

Smart speaker market’s potential

An Andes study done this year projected that the world’s tier-one online sellers may have more than 800 million active customers globally by 2022. Assuming a 30-percent adoption rate in the U.S. and 20-percent internationally, this would mean 55 million devices sold that year, the study concluded. Assuming a two year-replacement cycle, and US$75 average selling price, this would generate revenue of US$4 billion in 2022.
About the AndesCore N9 Family

The AndesCore N9 Family is intended for deeply embedded applications that require high-performance efficiency and optimal interrupt response features, including wireless networking and sensors as in microcontrollers, automotive electronics and industrial control systems.

The low-power N9 Family of processors features compact program size, low gate count, low interrupt latency and low-cost debug. The processor family provides superior performance and excellent interrupt handling response while meeting the challenges of low dynamic and static power constraints.

The AndesCore N9 Family of CPU cores implement v3, the patented AndeStar 32-bit RISC CPU architecture. Designers can configure certain parameters to adjust the desired CPU’s performance, power and gate count. For example, the N9 core can be configured with 16 or 32 general registers, two or three read ports on the register file, one or two write ports, a fast or a small multiplier, a 24-bit or 32-bit address space, and different bus (APB, AHB, AHB-Lite, or AXI) interfaces to connect to the rest of the system. Its bigger cousin N10 Family supports caches and an optional floating-point coprocessor.

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