* (3) integrated C64x+ cores running at 1 GHz each on a single die
* 3 GHz of raw DSP performance
* 24,000 MMACS (16-bit) in measured performance
* 100% code compatible with TI's single core DSPs based on C64x or C64x+ cores
* TI's SmartReflex technology reduces device power consumption by tweaking the core voltage once the chip is integrated into the system.
* Serializer/deserializer (SERDES) interfaces
* SGMII Ethernet MAC (EMAC)
* Antennae Interface (AIF)
* Serial Rapid I/O (SRIO)
* 32-kB of both L1 program and L1 data memory per core
* TI's fastest DDR2 memory interface running at 667 MHz on the chip