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Virtex-6 FPGA

Virtex-6 FPGA

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Product Specifications
  • Virtex-6 FPGA Domain Optimization 
    The Virtex- 6 FPGA family comprises three domain-optimized FPGA platforms that deliver different feature mixes to best address a variety of customer applications:


    Virtex-6 LXT FPGAs – optimized for applications that require high-performance logic, DSP, and serial connectivity with low-power GTX 6.5Gbps serial transceivers
    Virtex-6 SXT FPGAs – optimized for applications that require ultra high-performance DSP and serial connectivity with low-power GTX 6.5Gbps serial transceivers
    Virtex-6 HXT FPGAs – optimized for communications applications that require the highest-speed serial connectivity with up to 64 GTH serial transceivers supporting up to 11.2Gbps


    Among the high-performance applications for which Virtex-6 devices are ideally suited are:


    Wireless Infrastructure – The higher densities and increased performance of Virtex-6 FPGAs, coupled with optimized IP developed by Xilinx and its third-party network, enable advanced algorithms, such as crest factor reduction (CFR) and digital pre-distortion (DPD), that increase power amplifier efficiency by up to 40 percent. This significantly reduces operating expenses significantly, by as much as $18 million for a typical network operator running 10,000 base stations. Such levels of efficiency also lead to a reduction in carbon emissions of over 31,000 tons and are critical to delivering the ‘green' base-stations of the future. With exceptional features and industry-leading speed and power performance, Virtex-6 FPGAs make the ideal platform for next-generation 3GPP-LTE and LTE advanced base station development.


    Wired Networking – Increased consumption of digital content is straining existing network bandwidth and accelerating development of next-generation applications, such as 40Gbps/100+Gbps line cards, routers, switches, and high-density data ports for data centers. The Virtex-6 FPGA family includes optimized logic ratios, increased performance for wider internal datapaths, and multi-rate transceivers to deliver higher overall throughput at lower latency. Using the Virtex-6 FPGA family customers can implement an OTU (optical transport unit)-4 framing and enhanced forward error correction (EFEC) solution used in core networks. Optimized logic and transceiver ratios enable developers to implement the 100-Gigabit Ethernet (GE) to OTU-4 framer and critical EFEC using Virtex-6 FPGAs. Developers can replace costly, high-risk ASICs, while improving the flexibility of their proprietary, differentiated algorithms to extend the reach of their optical transport without using repeaters. Providing greater than 40 percent lower system power consumption, the Virtex-6 FPGA implementation can be deployed within existing infrastructure and power budgets, thereby dramatically reducing operating expenses.


    Broadcast Equipment – Virtex-6 FPGAs provide a fully programmable, cost-effective solution for meeting current and future broadcast requirements, while enabling differentiation through video quality. High-speed serial transceivers support SD/HD/3G-SDI and embedded audio for all types of broadcast applications. Fully integrated support for 10Gbps Ethernet enables bridging between broadcast and telecomm networks allowing fast access and retrieval of stored video content. Increased memory and DSP ratios enable real-time, uncompressed video processing at HD, 2K, and 4K resolutions. Optimized logic ratios and power management enable advanced H.264 and JPEG2000 encoding, all while reducing power and thermal management requirements for any given performance target. 


    Aerospace and Defense – Aerospace and defense designers are increasingly dependent upon FPGAs for high computational performance and reconfigurable computing in applications ranging from infrastructure communications to electronic warfare and image processing. Virtex-6 SXT FPGAs provide the industry's highest DSP bandwidth at over 1TMACS, by combining over 2000 advanced DSP slices with optimized ratios of logic, Block RAM, and distributed RAM. This computation bandwidth is augmented by over 450Gbps of serial bandwidth to move data on-chip and off-chip quickly and efficiently. All this computational capability is also fully scalable and optimized to reduce overall system power consumption by over 50 percent compared to previous generation technologies.