HD Video Frame Buffering Solution (AL460A-7&13-EVB-A0)
Key Specifications
This EVB board is designed for evaluating the AL460A HD-FIFO integrated chip. It has two embedded AL460A-7(-13)-PBF chips operating in parallel, expanding the bus width to 32-bits. Control signals and data bus signals are available on two 50-pin connectors; one connector is reserved for write controls and the input data bus; the other one is for read controls and the output data bus. A separate socket board is available to the user for connecting the module directly to an Altera Cyclone III FPGA board for any necessary solution verification/validation.
The AL460A is designed with a straightforward bus interface, reducing implementation and debugging efforts, and helping customers develop faster and more efficiently. This board is especially designed and optimized to be easily integrated as an add-on module on existing systems, significantly reducing interface engineering issues commonly found in retrofit efforts. This allows designers the luxury of being able to focus on core functionality and product quality.
Features:
* 256 Mbit density, 8M x 32-bit FIFO memory
* Maximum 150 MHz, 32-bit synchronous sequential read/write operations
* Maximum 4.8 Gbps throughput
* 3.3V power supply
* Programmable I/O control
* Supports double buffer mode (4M x32-bit upper and lower frames access)
* Selectable Polarity control
